1. Field of the Invention
The present invention relates to input stages for video processing, and more particularly to a calibration device for an input stage for processing a video signal.
2. Description of the Related Art
Input stages for processing video signals typically comprise a calibration circuit for calibrating downstream-located circuits in the receiver and for avoiding any saturation of these circuits.
A reference signal—corresponding to the coding of blacks—is used right after the line synchronization signal of the video signal, and the receiving circuit uses this reference to calibrate its internal circuits in order to avoid any saturation.
The performances required by video signal input circuits, together with the miniaturization of the latter and the reducing of supply voltage, enhance the weaknesses of known input stages.
FIG. 1 shows a traditional architecture of an input stage equipped with a so-called <<I-8I>> calibration circuit. FIG. 1 shows a coupling capacitor 102 that carries out continuous decoupling of line 101. Coupling capacitor 102 makes it possible to remove the continuous component from the input signal and can be charged and discharged by two power sources 104 and 105 which are controlled by two control signals (UP) and (Down) conveyed by lines 109 and 110, respectively. Downstream from the coupling capacitor, the video signal is amplified by a VGA amplifier 100 providing an output signal that is then digitally converted by means of an analog to digital ADC converter 107. ADC converter 107 provides samples of the video signal that are n-bit coded at the rhythm of a sampling clock. Digital samples are then suitably processed by means of a digital processing unit 108, which processing includes in particular calculating the gain of VGA amplifier 100 and clamp setting.
Generally, at reception of the reference signal corresponding to blacks, an average coding equal to 0 (on n-bit) is sought so as to benefit from all the dynamics of the coding system and to avoid any saturation. To this end, in the so called <<I-8I>> system, the digital processing carried out by the digital processing unit 108 provides a control signal, either UP on control line 109 or DOWN on control line 110 to control power source 104 or power source 105, respectively.
Although this known system provides satisfactory results for designing the input stages of conventional video receivers, it is not the case for modern architectures of video receivers due to the following reasons.
First, the <<I-8I>> system does not—and this is a known fact—allow to perfectly correct calibration error. It is noted that control from any of the control circuits—either UP or DOWN—always results in maintaining a variation between the perfect reference voltage and the ADC converter output code. Today, such lack of accuracy is crippling when compared with the performances required for modern video receivers.
Secondly, miniaturization of video circuits results in a continuous increase of the number of electronic components in semiconductor circuits. The size of elementary components, in particular MOS transistors, is reduced which then constrains to reducing supply voltages. This phenomenon is further aggravated by the development of portable or on board electronics, supplied with increasingly lower supply voltages.
It is not rare to feed video circuits with supply voltages that do not exceed 2 volts.
When supply voltage is reduced, it is clear that any calibration error of the video receiver input stage would reduce the remaining range for digital coding of the video signal thus increasing risks that the receiver saturates. Moreover, reducing the supply voltage also reduces the amplitude of signals that the circuits of the receiver can process. If amplification circuits known as <<track to track amplification circuits>> are used, linearity is affected and a crippling rate of distortion is introduced.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.